H Bharath Bhat
Student Intern | Siemens EDA
Student Intern at Siemens EDA with a background in hardware design and digital logic.
Skilled in SystemVerilog, UVM, and Ethernet protocol verification.
B.E. in Electronics and Communication Engineering from JSS Academy of Technical Education, Bengaluru.
SystemVerilog
Verilog
UVM
Python
C
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Experience
- Getting trained on APB Avery VIP.
- Built a UVM verification environment for a Memory Controller.
- Exploring Ethernet PHY configurations (1000BASE-T1 to 10G) and AXI/APB protocols.
SystemVerilogUVMAPB Avery VIP
- Guided by Dr. Sumit Kumar Mandal.
- Conducted comparative analysis of Matrix Multipliers.
- Focus on Energy Efficient Hardware Accelerators for ML Algorithms.
RTL DesignVerilogC
- Worked on Energy-Efficient Hardware Accelerators for Machine Learning.
- Contributed to IEEE Journal paper on Heterogeneous 2.5D Systems.
IEEE PublicationLLMHardware
Education
B.E. in Electronics & Communication
Aggregate: 8.83 CGPA
Dr. Vishnuvardhan Road, Bengaluru 560060
Pre-University, PCMB
Nagarbhavi, Bengaluru 560073
Secondary Schooling
Ullal, Bengaluru 560056
Certifications & Courses
Hardware & VLSI Design
Digital Design with Verilog
NPTEL
Apr 2024
(Link pending)
Programming & Cybersecurity
Programming, Data Structures & Algorithms using Python
NPTEL
Sep 2024
View Certificate
Tools & Web Technologies
Data Analytics Using Power BI
Vodafone Idea Foundation
Oct 2022
View Certificate
Workshops & Conferences