H Bharath Bhat
Product Engineer | Siemens EDA
Product Engineer at Siemens EDA with a background in hardware design and digital logic.
Skilled in SystemVerilog, UVM, and Ethernet protocol verification.
B.E. in Electronics and Communication Engineering from JSS Academy of Technical Education, Bengaluru.
SystemVerilog
Verilog
UVM
Python
C
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Experience
Product Engineer
March 2026 – Present
- Resolving technical queries and providing support for the Avery Verification IP (VIP)
for Ethernet protocols.
SystemVerilogUVMEthernet Protocol
Student Intern
July 2025 – Feb 2026
- Got trained on APB Avery VIP.
- Built a UVM verification environment for a Memory Controller.
- Exploring Ethernet PHY configurations (1000BASE-T1 to 10G) and AXI/APB protocols.
SystemVerilogUVMAPB Avery VIP
Research Intern
Sep 2024 – Jan 2025 | Hybrid
- Conducted comparative analysis of Matrix Multipliers.
- Guided by Dr. Sumit Kumar Mandal at the FIST Lab.
RTL DesignVerilogC
Research Intern
Nov 2023 – Apr 2024 | Onsite
- Worked on Energy-Efficient Hardware Accelerators for Machine Learning.
- Contributed to IEEE Journal paper on Heterogeneous 2.5D Systems.
IEEE PublicationLLMHardware
Education
B.E. in Electronics & Communication
Aggregate: 8.83 CGPA
Dr. Vishnuvardhan Road, Bengaluru 560060
Pre-University, PCMB
Nagarbhavi, Bengaluru 560073
Secondary Schooling
Ullal, Bengaluru 560056
Hobbies
Passionate about exploring nature and high-altitude trails. Notable
places I have trekked include:
Kumaraparvatha
Makalidurga
Bandaje Arbhi Falls
Narasimha Parvatha
Ramadevara Betta
Certifications & Courses
Hardware & VLSI Design
Verification Series Part 1 to 4
Udemy
Apr 2026
(Link pending)
Digital Design with Verilog
NPTEL
Apr 2024
(Link pending)
Programming & Cybersecurity
Programming, Data Structures & Algorithms using Python
NPTEL
Sep 2024
View Certificate
Tools & Web Technologies
Data Analytics Using Power BI
Vodafone Idea Foundation
Oct 2022
View Certificate
Workshops & Conferences
