Namaste🙏🏽, Myself Bharath, an aspiring VLSI Engineer with a strong background in hardware design and digital logic. I'm currently pursuing B.E. in Electronics and Communication Engineering from JSS Academy of Technical Education, Bengaluru. My expertise includes Verilog, C, and Python, along with hands-on experience in Xilinx Vivado, Cadence Genus, and Git.

• Research Intern · September 2024 - January 2025
  Indian Institute of Science, Bengaluru
  
  • Worked under the guidance of Dr. Sumit Kumar Mandal, Assistant Professor, Dept. of CSA, IISc on the Comparative analysis of Matrix Multipliers.
  • Skills: Verilog · Python · C
  
  
  Research Intern · November 2023 - April 2025
  
  • Worked on Energy-Efficient Hardware Accelerators for Machine Learning Algorithms in the Future Computing Systems (FIST) group within the Computer Science and Automation Department, IISc, Bengaluru.
  • My work also includes contributions to literature on Communication-aware Heterogeneous 2.5D Systems for Energy-efficient LLM Execution at Edge published at the IEEE Journal on Emerging and Selected Topics in Circuits and Systems.
  • Skills: Verilog · Python
  
  
  

• Bachelor of Engineering in Electronics and Communication Engineering · 2025
  JSS Academy of Technical Education, Bengaluru
  8.65/10 CGPA



• Pre-University, PCMB · 2020
  Mahesh PU College
  



• Secondary Schooling · 2018
  Vidyaniketan Public School